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INTEGRATED CIRCUITS
DATA SHEET
SAA4997H VErtical Reconstruction IC (VERIC) for PALplus
Preliminary specification File under Integrated Circuits, IC02 1996 Oct 24
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for PALplus
FEATURES * PALplus decoding * Vertical reconstruction * Quadrature mirror filter * Luminance and chrominance processing * Controlling. GENERAL DESCRIPTION
SAA4997H
The VErtical Reconstruction IC (VERIC) for PALplus (VERIC) is especially designed for use in conjunction with the Motion Adaptive Colour Plus And Control IC (MACPACIC) to decode the transmitted PALplus video signal in PALplus colour TV receivers. It provides the full vertical resolution of a PALplus picture from the letter box part and the decoded helper information.
QUICK REFERENCE DATA SYMBOL VDD Tamb supply voltage operating ambient temperature PARAMETER - 0 MIN. 70 MAX. 5.25 V C UNIT
ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION
SAA4997H QFP64 plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT319-2
1996 Oct 24
2
1996 Oct 24
handbook, full pagewidth
BLOCK DIAGRAMS
Philips Semiconductors
CLK_16B2 23 36
CLK_32B3
Y_FM23_0 to 7 8
8 F/C mode select
PIXEL SELECT
LUMINANCE PROCESSING (QM-FILTER)
Y_VE_0 to 7
8 DELAY COMPENSATOR
bypass
SAA4997H
8 8 PIXEL SELECT UV REFORMATTER 8 bypass 4 multi-PIP UV FORMATTER F/C
multi-PIP
U/V_FM23_0/1
4
CHROMINANCE PROCESSING (LP-FILTER)
4
VErtical Reconstruction IC (VERIC) for PALplus
U/V_VE_0/1
3
Y-control UV-control FM-control 5 Y - UV - FM CONTROL LOGIC BOUNDARY SCAN TEST 21 FILM EVEN_FIELD INTPOL 20 22 28 TDI 26 TCK 27 TMS
54 56 39 55 40 29 30
RSTR_FM23 OE_FM2 OE_FM3 RE_FM2 RE_FM3 TDO_VE TRSTN
VA_AI
19
LINE COUNTER DECODER
HREF_MA
17
PIXEL COUNTER DECODER
MGE443
Preliminary specification
SAA4997H
Fig.1 Block diagram.
ook, full pagewidth
Motion Adaptive Colour Plus and Control IC CLK_32B1
Vertical Reconstruction IC
1996 Oct 24
MACPACIC
CLK_16B1, 2, 3 CLK_32B1, 2, 3 TMS4C2970 8 Y_FM23_0 to 7 8 8 FM2 Y_MA_0 to 7 8 U_MA_0,1 V_MA_0,1 Y_VE_0 to 7 U_VE_0,1 V_VE_0,1 4 4 8 Y_TO_FM1_0 to 7 U_TO_FM1_0 - BB-decompanding - Motion adaptive luminance/chrominance separation CLK_16B2 CLK_32B3 HREF_MA VA_AI FILM EVEN_FIELD INTPOL TRSTN TDI TMS TCK TEST1-3 NC 3 11
MGE444
3
Y_FRONT[0 to 7] 3
VERIC
8
Y_ADC_0 to 7
Philips Semiconductors
TMS4C2970 8 4 4 4 U_FM23_0,1 V_FM23_0,1
8
Y_FM1_0 to 7
FM1
SWCK 4 TMS4C2970 8 8
SRCK
4
U_FM1_0,1 V_FM1_0,1
Y_VE_[0 to 7] U_VE_[0,1] V_VE_[0,1]
CLK_16 FM3 4
CLK_16B1
4
U_ADC_0,1 V_ADC_0,1
U_FRONT[0,1] V_FRONT[0,1] WE_FM2 U_TO_FM1_1(1) 4 4 - Inverse QMF reconstruction filter RSTW_FM23 V_TO_FM1_0(1) CLK_32B3 WE_FM3 V_TO_FM1_1(1) WE_FM1, RE_FM1 RST_FM14 WE_FM4, RE_FM4 VA_AI WE_MA HREF_MA FILM EVEN_FIELD INTPOL TDO_MA U_FM4_0,1 V_FM4_0,1 4 TMS4C2970 CLK_16B1 FM4 VDD1-4 VSS1-4
VDD1-5
5
VSS1-5
5
CLK_16
CLK_32
TDO_VE OE_FM2 OE_FM3 RE_FM2 RE_FM3 RSTR_FM23 - Vertical chrominance SRC
VA_FRONT WE_FRONT - Memory control - PALplus control 2 - Clock generation - Sync generation - SNERT interface 2
VErtical Reconstruction IC (VERIC) for PALplus
4
4
CLAMP
SNERT_DA
SNERT_CL
SNERT_RST
TRSTN
TDI
- FM2/FM3 read control
TMS TCK
TEST1-3
3
VERIC_AV_N(2)
U_TO_FM4_0,1 V_TO_FM4_0,1
(1) In case of stand alone MACPACIC the output signals are U_TO_FM1_1, V_TO_FM1_0 or V_TO_FM1_1; otherwise the output signals are WE_FM2, RSTW_FM23 or WE_FM3. (2) VERIC available: VERIC_AV_N is connected to VSS.
Preliminary specification
SAA4997H
Fig.2 Block diagram of the PALplus decoder module.
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for PALplus
PINNING SYMBOL Y_VE_1 Y_VE_0 U_VE_1 U_VE_0 V_VE_1 V_VE_0 VSS1 VDD1 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. HREF_MA n.c. VA_AI INTPOL FILM EVEN_FIELD CLK_16B2 VSS2 VDD2 TCK TMS TDI TDO_VE TRSTN n.c. n.c. TEST1 TEST2 TEST3 CLK_32B3 VSS3 1996 Oct 24 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 TYPE output output output output output output input input - - - - - - - - input - input input input input input input input input input input output input - - tbf tbf tbf input input buffered clock input (32 MHz) ground 3 5 luminance output data bit 1 luminance output data bit 0 chrominance output data bit 1 U-component chrominance output data bit 0 U-component chrominance output data bit 1 V-component chrominance output data bit 0 V-component ground 1 positive supply voltage 1 (+5 V) not connected not connected not connected not connected not connected not connected not connected not connected horizontal reference not connected vertical reference pulse related to output data INTPOL = 1: PALplus interpolation active DESCRIPTION
SAA4997H
INTPOL = 0: VERIC switched to bypass mode (standard signal) FILM = 0: CAMERA mode FILM = 1: FILM mode EVEN_FIELD = 0: odd field related to MACPACIC input data EVEN_FIELD = 1: even field related to MACPACIC input data buffered clock input (16 MHz) ground 2 positive supply voltage 2 (+5 V) boundary scan test clock input boundary scan test mode select input boundary scan test data input boundary scan test data output boundary scan test reset input not connected not connected test pins
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for PALplus
SYMBOL VDD3 OE_FM3 RE_FM3 V_FM23_1 V_FM23_0 U_FM23_1 U_FM23_0 Y_FM23_7 Y_FM23_6 Y_FM23_5 Y_FM23_4 Y_FM23_3 n.c. Y_FM23_2 Y_FM23_1 Y_FM23_0 RSTR_FM23 RE_FM2 OE_FM2 VDD4 VSS4 Y_VE_7 Y_VE_6 Y_VE_5 Y_VE_4 Y_VE_3 Y_VE_2 PIN 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 TYPE input output output input input input input input input input input input - input input input output output output input input output output output output output output output enable field memory 3 read enable field memory 3 chrominance input data bit 1 V-component chrominance input data bit 0 V-component chrominance input data bit 1 U-component chrominance input data bit 0 U-component Y input data bit 7 Y input data bit 6 Y input data bit 5 Y input data bit 4 Y input data bit 3 not connected Y input data bit 2 Y input data bit 1 Y input data bit 0 reset read field memory 2 and 3 read enable field memory 2 output enable field memory 2 positive supply voltage 4 (+5 V) ground 4 luminance output data bit 7 luminance output data bit 6 luminance output data bit 5 luminance output data bit 4 luminance output data bit 3 luminance output data bit 2 DESCRIPTION positive supply voltage 3 (+5 V)
SAA4997H
1996 Oct 24
6
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for PALplus
SAA4997H
52 Y_FM23_1 51 50 49 48 47 46 45 44 43
Y_VE_1 Y_VE_0 U_VE_1 U_VE_0 V_VE_1 V_VE_0 VSS1 VDD1 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c HREF_MA n.c. VA_AI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 INTPOL 20 FILM 21 EVEN_FIELD 22 CLK_16B2 23 VSS2 24 VDD2 25 TCK 26 TMS 27 TDI 28 TDO_VE 29 TRSTN 30 n.c. 31 n.c. 32
53 Y_FM23_0
handbook, full pagewidth
54 RSTR_FM23
56 OE_FM2
55 RE_FM2
63 Y_VE_3
62 Y_VE_4
61 Y_VE_5
64 Y_VE_2
60 Y_VE_6
59 Y_VE_7
57 VDD4
58 VSS4
Y_FM23_2 n.c. Y_FM23_3 Y_FM23_4 Y_FM23_5 Y_FM23_6 Y_FM23_7 U_FM23_0 U_FM23_1 V_FM23_0 V_FM23_1 RE_FM3 OE_FM3 VDD3 VSS3 CLK_32B3 TEST3 TEST2 TEST1
MGE442
SAA4997H
42 41 40 39 38 37 36 35 34 33
Fig.3 Pin configuration.
1996 Oct 24
7
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for PALplus
FUNCTIONAL DESCRIPTION Introduction As shown in Fig.2 the PALplus module consists of two special integrated circuits: * Motion Adaptive Colour Plus And Control IC (MACPACIC) * VErtical Reconstruction IC (VERIC) and four field memories TMS4C2970. The MACPACIC and the VERIC are intended to generate digitally decoded 50 Hz YUV signals. The MACPACIC performs the decompanding function for the helper lines and the motion adaptive luminance/chrominance separation. Furthermore, PALplus system controlling, memory controlling and clock generation are carried out in this circuit. The function of the VERIC is to reconstruct the separated 2 x 72 helper lines and the 430 main lines into a standard 576 lines frame according the PALplus system description "REV 2.0". Chrominance is converted from 430 lines to 576 lines using a vertical sample rate converter. The data of the VERIC are clocked out with 16 MHz. The Y : U : V bandwidth ratio is 4 : 1 : 1. The functional block diagram of the VERIC is shown in Fig.1. The device consists of 3 main parts: * Luminance processing * Chrominance processing * Controlling. The input data are delivered by the field memories FM2 and FM3, which include multiplexed first and second field data processed by the MACPACIC. The luminance and chrominance input data of the VERIC are clocked with 32 MHz (CLK_32B3). Internally the device operates at 32 or 16 MHz clock frequency. Luminance processing In the PALplus encoder the luminance signal is separated vertically into two sub-bands by a special Quadrature Mirror Filter (QMF). A vertical low-pass sub-band consists of the 430 main letter box lines per frame, and a vertical high-pass sub-band includes the 144 helper lines per frame. The used QMF technique has two advantages: * Essentially loss-free data processing * Cancellation of alias components in the main and helper signal in the decoder. 1996 Oct 24 8
SAA4997H
The luminance vertical conversion process in the decoder is complementary to that of the encoder. In the decoder the inverse QMF function is implemented to recombine the two separated sub-bands and to generate the original video signal with 576 active lines per frame. Each output line is calculated from up to seven input lines stored in line memories containing main or helper information. The various lines are multiplied by switched coefficients, changing every line within a sequence of four lines, depending on the specific mode (CAMERA or FILM). In case of standard PAL reception, the VERIC is switched to bypass mode controlled by the signal INTPOL. For multi-PIP processing the VERIC is also switched to bypass mode, but controlling of FM2/3 is different (see Fig.6). The total signal delay between the MACPACIC input and the VERIC output is one line for this mode. FM2/3 are driven with 32 MHz clock frequency. The non-multiplexed input data are clocked out with 16 MHz. Chrominance processing The chrominance processing is carried out by the vertical interpolation filter (poly phase filter). In CAMERA and FILM mode, intra-field vertical sample rate conversion is carried out. One output line is calculated out of three or four lines in CAMERA or FILM mode using different coefficients or passed through in bypass mode. Control functions The VERIC controller generates the necessary internal control signals for the line memories, formatters, reformatters, the selector signals for the multiplexers and the read signals for the field memories FM2/3. The system control input signals EVEN_FIELD, INTPOL and FILM are derived from the control part of the MACPACIC. The field selection information EVEN_FIELD is related to the input data of the MACPACIC and is adapted in the VERIC to its input data. The control functions are described in Tables 1 and 2. Table 1 EVEN_FIELD VALUE EVEN_FIELD = 1 EVEN_FIELD = 0 STATUS even field selected odd field selected
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for PALplus
Table 2 INTPOL and FILM VALUE INTPOL = 0 FILM = 0 INTPOL = 1 FILM = 0 INTPOL = 0 FILM = 1 INTPOL = 1 FILM = 1 STATUS bypass mode; standard signals interpolation active; PALplus CAMERA mode bypass mode; multi-PIP interpolation active; PALplus FILM mode Input/Output formats INPUT FORMATS Table 3 Delays FIELD first second CAMERA mode first second
SAA4997H
MODE FILM mode
VERIC I/O DELAY 2 lines 3 lines 3 lines 4 lines
Modes and delays The PALplus module can operate in two different hardware configurations: * Full PALplus configuration (MACPACIC and VERIC) * Stand alone MACPACIC. The vertical interpolation of the VERIC can be activated by the signal INTPOL depending on the PALplus signalling bits, transmitted in line 23 indicating the type of signal being received. However, the delay between input data of the MACPACIC and output data of the VERIC always has to be 1.5 fields. This is achieved with a suitable read timing of the field memories FM2 and FM3 controlled by VA_AI which is derived from the field length measurement in the MACPACIC. In case of INTPOL = LOW and additionally FILM = HIGH (FILM mode), the VERIC is switched to multi-PIP mode. In case the delay between input of the MACPACIC and output of the VERIC is one line (1024 CLK_16 periods). The line and pixel timings of the VERIC are shown in Figures 5 to 14.
The luminance input range of the main and helper signal has the following values: Main signal: black = 16, white = 191 (straight binary) Helper signal: 70, mid = 128 (straight binary) Chrominance format: 90, mid = 0 (two's complement). OUTPUT FORMATS Luminance format: black = 16, white = 191 (straight binary) Blanking: code 16 Chrominance format: 90, mid = 0 (two's complement) Blanking: code 0. Test activities The pins TEST1, TEST2 and TEST3 are provided to perform the IC test activities, such as scan test. The pins TRSTN, TDI, TMS, TCK and TDO_VE are intended for a boundary scan test.
1996 Oct 24
9
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for PALplus
DC CHARACTERISTICS Tj = 0 to 125 C SYMBOL Supply VDD IDD IDD(q) Inputs VIL VIH ILI Outputs VOL VOH IOL IOH LOW level output voltage HIGH level output voltage LOW level output current HIGH level output current IO = 20 A IO = 20 A VO = 0.5 V VO = VDD - 0.5 V - 4.0 4.0 - - - LOW level input voltage HIGH level input voltage input leakage current -0.5 2.0 - - - - supply voltage supply current quiescent supply current VDD = 5 V 4.75 - all inputs to VDD or VSS - 5.0 - - PARAMETER CONDITIONS MIN. TYP.
SAA4997H
MAX.
UNIT
5.25 80 100
V mA A
+0.8 VDD 1.0
V V A
0.1 - - -
V V mA mA
VDD - 0.1 -
AC CHARACTERISTICS Tj = 0 to 125 C SYMBOL PARAMETER CONDITIONS MIN. TYP. - - - 4.0 4.0 +10 - - - 4.0 4.0 50 MAX. UNIT
Clock timing CLK_32B3 (see Fig.4) TCY(32) tH tL tr tf fclk TCY(16) tH tL tr tf cycle time HIGH time LOW time rise time fall time deviation of clock frequency 28.1 9.2 9.2 2.0 2.0 -10 31.25 - - - - - - - - - - - ns ns ns ns ns %
Clock timing CLK_16B2 (see Fig.4) cycle time HIGH time LOW time rise time fall time duty cycle tH = ---tL 56.2 20.5 20.5 2.0 4.0 40 ns ns ns ns ns %
1996 Oct 24
10
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for PALplus
SYMBOL PARAMETER CONDITIONS MIN. TYP.
SAA4997H
MAX.
UNIT
Input data timing (CLK_32) tsu input data set-up time CLK_16B2 Y and UV_FM23 th(i) input data hold time CLK_16B2 Y and UV_FM23 Input control timing (CLK_16B2) HREF_MA, VA_AI, FILM, EVEN_FIELD AND INTPOL tsu th(i) input data set-up time input data hold time 4.5 0.1 - - - - ns ns 5.1 5.2 - - - - ns ns -4.7 -0.8 - - - - ns ns
Output data timing (CLK_16B2) Y AND UV_FM23 th(o) td(o) output data hold time output data delay time CL = 15 pF CL = 15 pF 8 - - - - 27 ns ns
Output control timing (CLK_32B3) OE_FM2, OE_FM3, RE_FM2, RE_FM3 AND RSTR_FM23 th(o) td(o) Delays tw(HREF) td(RE) tw(RE) td(VE)(MA) td(VE) td(VE) td(RSTR) td(FM2) HREF_MA pulse width delay RE_FM2/3 to HREF_MA RE_FM2/3 pulse width delay HREF_MA to YUV_VE delay data input to output delay data input to output delay RSTR delay FM2 input to output multi-PIP multi-PIP multi-PIP - - - - - - - - 60 x TCY(16) 127 x TCY(32) - - ns ns ns ns ns ns ns ns output data hold time output data delay time CL = 15 pF CL = 15 pF 5 - - - - 20 ns ns
1680 x TCY(32) - 80 x TCY(16) 16 x TCY(16) 2 x TCY(16) - - -
2016 x TCY(32) - 2040 x TCY(32) -
1996 Oct 24
11
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for PALplus
TIMING
SAA4997H
handbook, full pagewidth
tr CLK 90% 50% 10% tH
tf
tL
DATA/CONTROL
Dn th(o) td(o)
XX
D(n+1) th(i) tsu
MGE445
Data input: CLK = CLK_32B3 Data output: CLK = CLK_16B2 Control input: CLK = CLK_16B2 Control output: CLK = CLK_32B3
Fig.4 Data/control input/output set-up and hold timing.
1996 Oct 24
12
1996 Oct 24
handbook, full pagewidth
Philips Semiconductors
CLK_32B3
CLK_16B2
tw(HREF)
HREF_MA
VErtical Reconstruction IC (VERIC) for PALplus
td(RE)
tw(RE)
13
1 x TCY(32) td(VE) td(VE)(MA)
RE_FM2/3
Y(U/V)_FM23
Y(U/V)_VE
MGE446
Preliminary specification
SAA4997H
Fig.5 Pixel timing (except multi-PIP mode).
1996 Oct 24
handbook, full pagewidth
Philips Semiconductors
CLK_16B2
CLK_32B3
VA_AI td(RSTW)
RSTW_FM2 td(RSTR)
VErtical Reconstruction IC (VERIC) for PALplus
RSTR_FM2
14
1 3 td(MA) 1 td(FM2) 1 1 2 2 3 3 1 2 3 3 2 2 1 td(VE) 1024 pixels 2 3
MGE447
YUV_ADC
YUV_MA
YUV_FM2
YUV_VE
WE_FM2 and RE_FM2 are constant HIGH; YUV_MA = MACPACIC input.
Preliminary specification
SAA4997H
Fig.6 Pixel timing multi-PIP mode (MACPACIC input to VERIC output).
1996 Oct 24
handbook, full pagewidth
Y1A Y1B Y2A Y2B Y3A Y3B Y4A Y4B Y5A Y5B Y6A Y6B Y7A Y7B Y8A Y8B Y839 B
Philips Semiconductors
CLK_32B3
RE_FM2/3
Y_FM23(0-7)
Y0A
Y0B
VErtical Reconstruction IC (VERIC) for PALplus
U_FM23_1
U70A U50A U30A U10A U70B U50B U30B U10B U74A U54A U34A U14A U74B U54B U34B U14B U78A U58A
U1 836B
15 Fig.7 Input data timing (except multi-PIP mode).
U_FM23_0
U60A U40A U20A U00A U60B U40B U20B U00B U64A U44A U24A U04A U64B U44B U24B U04B U68A U48A
U0 836B
V_FM23_1
V70A V50A V30A V10A V70B V50B V30B V10B V74A V54A V34A V14A V74B V54B V34B V14B V78A V58A
V1 836B
V_FM23_0
V60A V40A V20A V00A V60B V40B V20B V00B V64A V44A V24A V04A V64B V44B V24B V04B V68A V48A
V0 836B
MGE448
V60A
input signal
bit
field word
Preliminary specification
SAA4997H
1996 Oct 24
handbook, full pagewidth
16 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 16 Y 839
Philips Semiconductors
CLK_16B2
Y_VE(0-7)
VErtical Reconstruction IC (VERIC) for PALplus
U_VE_1
0 U70 U50 U30 U10 U74 U54 U34 U14 U78
U1 836
0
16
0 U60 U40 U20 U00 U64 U44 U24 U04 U68 U0 836 0 0 V70 V50 V30 V10 V74 V54 V34 V14 V78 V1 836 0 0 V60 V40 V20 V00 V64 V44 V24 V04 V68 V0 836 0
MGE449
U_VE_0
V_VE_1
V_VE_0
V60
input signal
word
bit
Preliminary specification
SAA4997H
Fig.8 Output data timing.
1996 Oct 24
handbook, full pagewidth
Philips Semiconductors
20 lines
VA_AI 146 lines 145 lines
multiplexed active lines from FM23
YUV_FM23(0-7)
166/478 167/479 311/623
21/333
VErtical Reconstruction IC (VERIC) for PALplus
OE_FM2
17
23 24 25 26 27 166 167
RE_FM2
OE_FM3
RE_FM3
Y/UV_VE
21
22
311
MGE450
Preliminary specification
SAA4997H
Fig.9 Line read timing FM2/3 bypass mode standard signal, first field.
1996 Oct 24
handbook, full pagewidth
Philips Semiconductors
19 lines field B
VA_AI 146 lines 145 lines
multiplexed active lines from FM23
YUV_FM23(0-7)
166/478 167/479 311/623
21/333
VErtical Reconstruction IC (VERIC) for PALplus
OE_FM2
18
335 336 337 338 339 478 479
RE_FM2
OE_FM3
RE_FM3
Y/UV_VE
333
334
623
MGE451
Preliminary specification
SAA4997H
Fig.10 Line read timing FM2/3 bypass mode standard signal, second field.
full pagewidth
1996 Oct 24
25 26 27 161 162 163 164 165 166 167 302 303 304 305 306 307 308 309 310
M11,10 M9,8 H3,4 UV11,10
Philips Semiconductors
VERIC line counter
21
22
23
24
Y_FM23 (1)
M3,2
H1,2
M5,4
M7,6
U/V_FM23
UV3,2
UV5,4 UV7,6 UV9,8
OE_FM3
VErtical Reconstruction IC (VERIC) for PALplus
RE_FM3
19
25 26 27 161 162 163 164 165 166 167 302 303 304 305 306 307 308 309 310
MGE452
OE_FM2
RE_FM2
Y/UV_VE
23
24
(1) M = main line and H = helper line.
Preliminary specification
SAA4997H
Fig.11 Line read timing FM2/3 CAMERA mode, first field.
1996 Oct 24
handbook, full pagewidth
Philips Semiconductors
VERIC line counter 24 25 26 160 161 162 163 164 165 166 301 302 303 304 305 306 307 308 309 310
M11,10 H3,4
20
21
22
23
Y_FM23(0-7) (1)
M3,2 M5,4
H1,2
M7,6 M9,8
U/V_FM23(0-1)
9,8 11,12
3,2
5,4
7,6
VErtical Reconstruction IC (VERIC) for PALplus
OE_FM3
20
337 338 339 476 477 478 479 480 481 482 614 615 616 617 618 619 620 621 622 623
MGE453
RE_FM3
OE_FM2
RE_FM2
Y/UV_VE
336
(1) M = main line and H = helper line.
Preliminary specification
SAA4997H
Fig.12 Line read timing FM2/3 CAMERA mode, second field.
1996 Oct 24
handbook, full pagewidth
M11,10 M7,6 M9,8 H3,4 UV11,10
Philips Semiconductors
Y_FM23 (1)
M3,2
H1,2
M5,4
U/V_FM23
UV3,2
UV5,4 UV7,6 UV9,8
OE_FM3
VErtical Reconstruction IC (VERIC) for PALplus
21
25 26 27 28 162 163 164 165 166 167 168 303 304
RE_FM3
OE_FM2
RE_FM2
Y/UV_VE
23
24
305
306
307
308
309
310
MGE454
(1) M = main line and H = helper line.
Preliminary specification
SAA4997H
Fig.13 Line read timing FM2/3 FILM mode, first field.
1996 Oct 24
handbook, full pagewidth
M11,10 M9,8 H3,4
Philips Semiconductors
Y_FM23(0-7) (1)
M3,2
H1,2
M5,4
M7,6
OE_FM3
VErtical Reconstruction IC (VERIC) for PALplus
RE_FM3
22
338 339 340 474 475 476 477 478 479 480 615 616 617 618 619 620 621 622 623
MGE455
OE_FM2
RE_FM2
Y/UV_VE
336
337
(1) M = main line and H = helper line.
Preliminary specification
SAA4997H
Fig.14 Line read timing FM2/3 FILM mode, second field.
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for PALplus
PACKAGE OUTLINE QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SAA4997H
SOT319-2
c
y X
51 52
33 32 ZE
A
e E HE A A2 A1
Q (A 3) Lp L detail X
pin 1 index
wM bp
64 1 wM D HD ZD 19
20
e
bp
vMA B vM B
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.20 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.50 0.35 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 1 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 Q 1.4 1.2 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT319-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
1996 Oct 24
23
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for PALplus
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9398 510 63011). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.
SAA4997H
If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1996 Oct 24
24
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for PALplus
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA4997H
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1996 Oct 24
25
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for PALplus
NOTES
SAA4997H
1996 Oct 24
26
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for PALplus
NOTES
SAA4997H
1996 Oct 24
27
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/1200/01/pp28
Date of release: 1996 Oct 24
Document order number:
9397 750 01423

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